Electronic device and methods to customize electronic device electromagnetic emissions

ABSTRACT

A semiconductor device comprises a semiconductor substrate, one or more circuits disposed on the semiconductor substrate, and a modification of any one of hardware, software or firmware of the electronic device that generates emission of electromagnetic energy from the semiconductor device with desired characteristic(s), without changing a designed interface functionality of the semiconductor device. Method are also provided for modifying the semiconductor device and identifying modified semiconductor device.

CROSS-REFERENCE TO RELATED APPLICATIONS

The present application is related to and claims priority fromprovisional U.S. patent application No. 62/387/820, titled“Harnessed-unintended Emissions Generation, Detection, and Utilization”and filed Jan. 6, 2016 by inventors Walter John Keller, AlexanderWilliam Keller, Andrew Richard Portune and Todd Eric Chornenky, theentire contents of which are hereby incorporated by reference thereto.

This document incorporates by reference the entire contents ofdisclosures and/or teachings of the following documents: U.S. Pat. No.7,515,094 entitled “Advanced electromagnetic location of electronicequipment”; U.S. Pat. No. 8,063,813 entitled “Active improvisedexplosive device (IED) electronic signature detection”; U.S. Pat. No.8,537,050 entitled “Identification and analysis of source emissionsthrough harmonic phase comparison”; U.S. Pat. No. 8,643,539 entitled“Advance manufacturing monitoring and diagnostic tool”; U.S. Pat. No.8,825,823 entitled “System and method for physically detecting,identifying, diagnosing and geolocating electronic devices connectableto a network”; U.S. Pat. No. 9,205,270 entitled “METHOD AND APPARATUSFOR THE DIAGNOSIS AND PROGNOSIS OF ACTIVE IMPLANTS IN OR ATTACHED TOBIOLOGICAL HOSTS OR SYSTEMS”; U.S. Pat. No. 9,059,189 entitled“INTEGRATED CIRCUIT WITH ELECTROMAGNETIC ENERGY ANOMALY DETECTION ANDPROCESSING”; US Pub. 2012-0226463 entitled “SYSTEM AND METHOD FORPHYSICALLY DETECTING COUNTERFEIT ELECTRONICS”; US Pub. 2013-0229310entitled “SYSTEM AND METHOD FOR GEO-LOCATING AND DETECTING SOURCE OFELECTROMAGNETIC EMISSIONS”; US Pub. 2013-0328710, entitled “Method andApparatus for Detection and Identification of Counterfeit andSubstandard Electronics”; U.S. Pat. No. 9,285,463 entitled “Method andApparatus for battle damage assessment of electric or electronicdevices”); US Pub. 2015-0137830 A1 entitled “Method and Apparatus forDetection and Identification of Counterfeit and SubstandardElectronics”, US Pub. 2014-0218229 Al entitled “Advance ManufacturingMonitoring and Diagnostic Tool”; PCT/US2015/014765 entitled “METHOD ANDAPPARATUS FOR DETECTION AND IDENTIFICATION OF COUNTERFEIT ANDSUBSTANDARD ELECTRONICS” and US Pub. 2015-0009073 A1 entitled “Systemand Method for Physically Detecting, Identifying, Diagnosing andGeolocating Electronic Devices Connectable to a network”.

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BACKGROUND

1. Technical Field

The subject matter relates to electronic devices. It further relates togeneration and processing of emissions from electronic device.

2. Description of Related Art

The following background information may present examples of specificaspects of the prior art (e.g., without limitation, approaches, facts,or common wisdom) that, while expected to be helpful to further educatethe reader as to additional aspects of the prior art, is not to beconstrued as limiting the present invention, or any embodiments thereof,to anything stated or implied therein or inferred thereupon.

Conventionally employed solutions to wirelessly transmit a signal or astate of an electronic device can employ complex circuits configured tocommunicate with the electronic device from which the state orinformation is stored. Such radio frequency (RF), audio, infra-red (IR),light or other electromagnetic circuit control means can be typicallyemployed and their intended frequency signal allocation, configurationand design is specified to conform to the electronics and commercial FCCfrequency allocations recognized worldwide. These conventionallyemployed solutions can typically require the choice and pre-calculatedcircuitry tolerances, power levels, transmission range calculations andpart specifications. These conventionally employed solutions may notemploy an ad-hoc design, nor do they utilize existing hardware and/orsoftware resource. The above described solutions typically employ arecognized standard modulation means. Further, the above describedsolutions typically require additional hardware expense. Further, theabove described solutions typically require the addition of asubstantial number of circuit elements dedicated to creating thetransmit signal, typically more than 10. The conventional electronicdevices cannot be easily and quickly modified and/or retrofitted intoexisting hardware or software. The conventional solutions cannot beemployed outside legally allocated frequency bands without powerlimitations and may interfere with other sensitive electronic equipment.

BRIEF DESCRIPTION OF THE DRAWINGS

The accompanying drawings are incorporated in and constitute part of thespecification and illustrate various embodiments. In the drawings:

FIG. 1 illustrates an exemplary system of generating and processing RFemissions from an electronic device;

FIG. 2 illustrates an enlarged view of the electronic device of FIG. 1;

FIG. 3 illustrates a flowchart of an exemplary method of generating RFemissions from a hardware modification;

FIG. 4 illustrates a flowchart of an exemplary method of generating RFemissions from a software modification;

FIGS. 5A and 5B illustrate flowcharts of exemplary methods of detectingand determining desired RF signal characteristics due to hardware,software or firmware modifications;

FIGS. 6A-6B illustrates an exemplary spectrum change as a result of amodification causing a desired RF emission;

FIG. 7 illustrates an exemplary hardware configuration to receive anddecode RF emission data;

FIG. 8 illustrates an exemplary embodiment wherein the electromagneticemission is generated by modification(s) to a computer, Printed CircuitBoard (PCB) assemblies or Multi-chip modules;

FIG. 8A illustrates an exemplary embodiment wherein the electromagneticemission is generated by modification(s) to a printed circuit board(PCB);

FIG. 9 illustrates an exemplary assembly source code computer languagesegment of instructions which generate desired RF emissions undercontrolled conditions;

FIG. 10A-10D illustrate an VHDL firmware exemplary ring oscillator,logic diagram representations of the exemplary ring oscillator, andhardware microcircuit of the exemplary ring oscillators;

FIG. 11 illustrates an exemplary nanotube constructed hardware ringoscillator;

FIG. 12 illustrates an example of a hardware modification of theelectronic device of FIGS. 1-2;

FIG. 13 illustrates an example of a hardware modification of theelectronic device of FIGS. 1-2;

FIG. 14 illustrates an example of a hardware modification of theelectronic device of FIGS. 1-2;

FIG. 15 illustrates an example of a hardware modification of theelectronic device of FIGS. 1-2;

FIG. 16 illustrates an example of a hardware modification of theelectronic device of FIGS. 1-2;

FIG. 17 illustrates an example of a hardware modification of theelectronic device of FIGS. 1-2;

FIG. 18 illustrates an example of a hardware modification of theelectronic device of FIGS. 1-2;

FIG. 19 illustrates an example of a hardware modification of theelectronic device of FIGS. 1-2;

FIG. 20 illustrates an example of a hardware modification of theelectronic device of FIGS. 1-2;

FIG. 21 illustrates an example of a hardware modification of theelectronic device of FIGS. 1-2;

FIG. 22 illustrates an example of a hardware modification of theelectronic device of FIGS. 1-2;

FIG. 23 illustrates an example of a hardware modification of theelectronic device of FIGS. 1-2;

FIG. 24 illustrates an example of a hardware modification of theelectronic device of FIGS. 1-2;

FIG. 25 illustrates an example of a hardware modification of theelectronic device of FIGS. 1-2;

FIG. 26 illustrates an example of a hardware modification of theelectronic device of FIGS. 1-2;

FIG. 27 illustrates an example of a hardware modification of theelectronic device of FIGS. 1-2;

FIG. 28 illustrates an example of a hardware modification of theelectronic device of FIGS. 1-2;

FIG. 29 illustrates an example of a hardware modification of theelectronic device of FIGS. 1-2;

FIG. 30 illustrates an example of a hardware modification of theelectronic device of FIGS. 1-2; and

FIGS. 31A-D illustrate an example of a hardware modification of theelectronic device of FIGS. 1-2 a containing an RS Flip-Flop with anemission enhancement antenna stub.

DETAILED DESCRIPTION OF EXEMPLARY EMBODIMENTS

Prior to proceeding to the more detailed description of the presentinvention, it should be noted that, for the sake of clarity andunderstanding, identical components which have identical functions havebeen identified with identical reference numerals throughout the severalviews illustrated in the drawing figures.

The following detailed description is merely exemplary in nature and isnot intended to limit the described examples or the application and usesof the described examples. As used herein, the words “example”,“exemplary” or “illustrative” means “serving as an example, instance, orillustration.” Any implementation described herein as “example”,“exemplary” or “illustrative” is not necessarily to be construed aspreferred or advantageous over other implementations. All of theimplementations described below are exemplary implementations providedto enable persons skilled in the art to make or use the embodiments ofthe disclosure and are not intended to limit the scope of thedisclosure, which is defined by the claims.

The term “or” when used in this specification and the appended claims isnot meant to be exclusive; rather the term is inclusive, meaning eitheror both.

The term “couple” or “coupled” when used in this specification andappended claims refers to an indirect or direct physical connectionbetween the identified elements, components, or objects. Often themanner of the coupling will be related specifically to the manner inwhich the two coupled elements interact.

The term “directly coupled” or “coupled directly,” when used in thisspecification and appended claims, refers to a physical connectionbetween identified elements, components, or objects, in which no otherelement, component, or object resides between those identified as beingdirectly coupled.

The term “operatively coupled,” when used in this specification andappended claims, refers to a physical connection between identifiedelements, components, or objects, wherein operation of one of theidentified elements, components, or objects, results in operation ofanother of the identified elements, components, or objects.

It is to be understood that the singular forms “a,” “an,” and “the”include plural referents unless the context clearly dictates otherwise.Thus, for example, reference to “a circuit” includes reference to one ormore of such circuits.

It is to be understood that electromagnetic emissions may be, but is notlimited to radio frequency (RF) emissions, microwave emissions,millimeter wave emissions and terahertz wave emissions. It is further tobe understood that the term “communication” implies conveyance ofinformation ranging from very simple yes/no existence or power on/offstatus to detailed data with complex multiple state and data content.Further, it is to be understood that the term ‘Outside World’ is anydevice or individual outside of the RF detection and decoding apparatus.

The terms and words used in the following description and claims are notlimited to the bibliographical meanings, but, are merely used by theinventor to enable a clear and consistent understanding of theinvention. Accordingly, it should be apparent to those skilled in theart that the following description of exemplary embodiments of thepresent invention are provided for illustration purpose only and not forthe purpose of limiting the invention as defined by the appended claimsand their equivalents.

Furthermore, there is no intention to be bound by any expressed orimplied theory presented in the preceding technical field, background,or the following detailed description. It is also to be understood thatthe specific devices and processes illustrated in the attached drawings,and described in the following specification, are simply examples of theinventive concepts defined in the appended claims. Hence, specificdimensions and other physical characteristics relating to the examplesdisclosed herein are not to be considered as limiting, unless the claimsexpressly state otherwise.

The particular embodiments of the present disclosure generally providedevices, apparatuses, and methods directed to generating and processingemissions of electromagnetic energy.

In particular embodiments, a semiconductor device comprises asemiconductor substrate, one or more circuits disposed on thesemiconductor substrate, and particular embodiments employ a means formodifying, without changing a designed interface functionality of saidsemiconductor device, characteristic(s) of an electromagnetic energyemittable from the semiconductor device.

In some embodiments, a hardware, software or firmware can be modified togenerate RF emission of varying information content ranging from asimple device On/Off to a complex RF emission(s), wherein complexemissions may be comprised and reliably decodable into a significantnumber of data bits, typically over 8 bits.

Now in reference to Figures, FIG. 1, illustrates an exemplary embodimentof an apparatus (system) 180 directed towards receiving and processingelectromagnetic energy emissions 102, 104 from an electronic device 100.In this exemplary embodiment, the electromagnetic energy emission 102 or104 is in a radio frequency (RF) range and defines a RF signal. Theelectronic device 100 is illustrated as being mounted on a printedcircuit board (PCB) 160 and is powered, during operation, through one ormore input/output (I/O) pins 108. The apparatus 180 comprises an antenna106 to capture or receive emitted RF signal. The apparatus 180 alsocomprises a receiver 118 and the antenna 106 is illustrated as beingcoupled to the receiver 118. The receiver 118 at least comprises and/oris represented by a low noise amplifier (LNA) 122. The antenna 106 canbe coupled to the LNA 122 through a conductor cable 120. The RF signalacquired by antenna 106 is transmitted through the conductor cable 120to (LNA) 122 where it is amplified to a level suitable for processing.The apparatus 180 also comprises a control unit 126. The control unit126 is coupled to the receiver 118, for example with another conductorcable 124. Amplified RF signal is transmitted through the cable 124 tothe control unit 126. The control unit 126 is configured to processand/or examine the data within the amplified RF signal in accordancewith a predetermined logic. The results of the processing and/orexamination of the RF signals can be optionally conveyed using acommunication line 130, which may also be a wireless communicationmeans, to the outside world 140 where it is acted upon or optionallyignored. The outside world 140 may log the events sent to it from thecommunication line over 130, may generate an alarm or alert based on theevents sent to it over the communication line 130, or may furtherprocess the data within the RF signal sent over the communication line130.

The control unit 126 is shown as of a microprocessor type comprising oneor more processors 127 and non-transitory tangible computer readablemedium and/or tangible computational medium comprising algorithms and/orexecutable instructions, that cause the one or more processors 127 toprovide elements of various embodiments. One example of such elementscan be processing of data or information contained within RF emissionsignal from the electronic device 100. The algorithms and/or executableinstructions are stored in a non-transitory storage medium 128. Thecontrol unit 126 may be provided as a custom manufactured controller, aprogrammable logic controller (PLC), a computer, a System On Chip (SoC),a Multi-Chip Module (MCM) or a portable device that includes, but is notlimited to, a cell phone, a smart phone, a portable personal computer, apad, a tablet or the like.

The control unit 126 may be configured as a simple bandpass filter tunedto the modified frequency of emission of interest.

Tangible computer readable medium means any physical object or computerelement that can store and/or execute computer instructions. Examples oftangible computer readable medium include, but not limited to, a compactdisc (CD), digital versatile disc (DVD), blu-ray disc (BD), usb floppydrive, floppy disk, random access memory (RAM), read-only memory (ROM),erasable programmable read-only memory (EPROM), optical fiber, etc. Itshould be noted that the tangible computer readable medium may even bepaper or other suitable medium in which the instructions can beelectronically captured, such as optical scanning. Where opticalscanning occurs, the instructions may be compiled, interpreted, orotherwise processed in a suitable manner, if necessary, and then storedin computer memory. Alternatively, tangible computer readable medium maybe a plugin or part of a software code that can be included in, ordownloaded and installed into a computer application. As a plugin, itmay be embeddable in any kind of computer document, such as a webpage,word document, pdf file, mp3 file, etc.

FIG. 2 illustrates an enlarged view of the electronic device of FIG. 1,albeit with more pins 108. More particularly, the electronic device 100is illustrated as an integrated circuit (IC) device. The electronicdevice 100 can be also any one of a field-programmable gate array(FPGA), an application-specific integrated circuit (ASIC), a multichipmodule, a logic gate, a SoC, an MCM or any combination thereof. As isconventional, the IC 100 comprises a package (casing) 201, the abovementioned I/O pins 108 that extend from the package (casing) 201, a die220 comprising a substrate 222, one or more circuits or circuit elements200, 202 on the substrate 222, leads 210 each being electrically coupledto a respective I/O pin 108, and bonding wires 212 coupling the die 220to each lead 210. The die 220 with the one or more circuit element 200,202 can be also referred to as a chip. The exact structure of the die220 is omitted herein for the sake of brevity. Some I/O pin(s) 108 aregenerally configured to provide power (voltage) and/or clock signal tothe chip 220.

The circuit (logic) element 200, 202 is to be understood as anyconstituent part of a circuit that contributes directly to its operationand performs a definable function. Examples can include transistors,resistors, capacitors, inductors, and interconnections. The package 201is to be understood as an enclosure for one or more semiconductor chips(dice), film elements, or other components, that allows electricalconnection and provides mechanical and environmental protection.

The substrate 222 of the die 220 may include a silicon substrate, asilicon germanium (SiGe) substrate, a bulk semiconductor substrate, astrained semiconductor substrate, a compound semiconductor substrate, asilicon-on-insulator (SOI) substrate or other commonly or uncommonlyused semiconductor substrates.

FIG. 2 also illustrates that IC 100 generates RF emissions 102 from thecircuit element 200 that contain different signature characteristicsthan RF signature characteristics from the emissions 104 from one ormore I/O pins 108. It is also contemplated that each pin 108 cangenerate RF emissions with different signature characteristics due tospecific application. For example, different voltage may be present ateach I/O pin 108. FIG. 2 further illustrates that IC 100 can generateelectromagnetic energy emission(s) 206 from the lead 210 orelectromagnetic energy emission(s) 208 from each bonding wire 212. Morethan one die can be provided within the IC 100, for example such as anadditional die 250 containing one or more circuit element 252 andcoupled with a lead 224 and bonding wire 226 to the I/O pin 108.Similarly, the die 250 can generate RF emissions 102A from the one ormore circuit elements 252, emissions 107 from the I/O pin 108, RFemissions 254 from the lead 224 and even RF emissions 256 from thebonding wire 226.

The die 220, 252 or the IC 100 can also comprise redistribution layer(RDL) not shown.

Furthermore, although the IC 100 is illustrated as having I/O pins 108,such I/O pins 108 can be replaced with solder bumps (not shown) or ballgrid array (not shown) for I/O purposes to the IC 100. The pins 108,solder bumps (not shown) and ball grid array (not shown) provide meansfor attaching the IC 100 to a substrate, for example such as a printedcircuit board.

The RF emissions 102 originating from the one or more circuit element200, 202 inside the die 220, or RF emissions 104 originating from theI/O pin(s) 108, RF emissions 206 originating from the leads 210 or RFemissions 208 from the bonding wires 212, are emitted based on the logicconfigurations contained in the portion of the chip at location 200, or202. These logic configurations at locations 200 or 202 may be a ringoscillator, or other circuit or a circuit element that may contain arepeating, semi-repeating, or iterative pattern of operation. The sizeof a possible ring oscillator may be controlled by state inputs to theRF generation circuit and the emitted RF signal may be modified and itsmodified state may be received, processed and communicated by theapparatus 180.

FIG. 3 illustrates a flowchart of an exemplary method to create orgenerate a modified RF emission with desired (signature)characteristic(s) within hardware or firmware logic of the chip. In step300, hardware design of the existing die or chip is acquired. In step302, the existing chip hardware design is modified to include additionalor new RF emission element(s) into one or more circuits, for examplesuch as the circuit/circuit elements 200, 202 or 252. The modifiedcircuit at locations 200, 202, 252 would now be operable to generate thedesired RF characteristic(s). The examples of these additional or new RFemission element(s) will be described further in this document. In step304, the new design is instantiated into a created die, and typicallyplaced in a package, such as IC 100, and can be later installed on a PCB160 with the PCB 160 being integrated into a higher level assembly, forexample such as a computer. In step 306, at least power and necessaryclock signal(s) are connected, generally during operation or testing, torespective pins of the chip 100 containing the newly created die. Instep 308, the modified region, for example such as the modified circuit200 is activated, and begins emitting RF emission 102 with desiredcharacteristic(s). Such RF emissions with desired characteristic(s) canbe characterized as “pseudointended” emissions due to a forced or apredetermined nature of their generation. Further, such emissions can beconducted emissions which are coupled into the traces, interconnects,wiring, pins and/or external traces or wiring for further emission andemission strength. In optional step 310 the RF emission, such as any oneof RF emissions 102, 102A, 104, 206, 208, and 256 is acquired orharvested, for example by an antenna 106 of FIG. 1, and processed by theapparatus 180 to extract the data from RF signal. Since, the chip 100will generate any of the above RF emissions when power signal or powerand clock signals are connected to respective pin(s), the chip 100 doesnot have to be fully operational. In other words, the chip 100 willgenerate RF emissions 102, 104, even when the circuits or circuitelements 200, 202 and/or 252 are not energized or operate. Thus, the RFemissions from the chip 100 under these conditions can be considered asunintended emissions. However, the RF emissions can be also generated,captured and processed when the chip 100 is fully operational. Thus, theRF emissions from the operating chip 100 can be considered as intendedemissions.

With further particular reference to FIG. 3, therein is also shown astep 312 of acquiring an existing hardware description language file,such as VHDL or Verilog logic file to be modified to add a desired RFemission. In step 314, the existing logic files obtained in step 312 aremodified to contain a RF emission emitting logic configuration, forexample such as a ring oscillator. In step 316, the modified VHDL issuitably compiled on the vendor's VHDL to Bit file translation softwarefor the device it is to run on and loaded into the chip 100 to beexecuted. In step 318, the operation of the chip 100, for example suchas FPGA, is started, causing step 320 to energize the logic circuit 200and emit RF emissions. Again, in the optional step 310, the RF emissionsmay be acquired and processed for indication of FPGA internal state,configuration or authenticity, and then optionally communicated to theexternal world 140, where a computer, individual human, or transmittermay then use, or perform a data logging operation for example. The VHDLcode could represent a binary counter, a ring oscillator, or typically asimilar variety of logic circuits which substantially repeat theiroperation. Based on the state of binary input lines, the specific endcount or preset start count may be established, modifying the operationof a binary counter, thus modifying the RF based on the state of binaryinput lines.

FIG. 4 illustrates a flowchart of an exemplary method to create a RFemission with desired characteristic(s) within a software entity insteadof a hardware entity of FIG. 3. In step 400, an existing source codemeant to be running inside of the chip 100 is acquired. In step 402, thesource code acquired in step 400 is modified to add RF emissiongenerating code or logic, for example such as an assembler code 900shown in FIG. 5. The no-optimization option of the assembler or compilercan be enabled to prevent optimizing redundant operations away in thefinal compiled version of the object code resulting from the assembledor compiled code. In step 404, the program is modified and compiled andexecutable code generated to contain both the new RF emissionsgenerating code and the original code acquired in 400. In step 406, thenewly generated program is executed, for example on a central processingunit (CPU) such as 100, capable of running the executable codegenerated. In step 408, the modified region containing the new codewhich creates a RF emission is run, and RF emission with desiredcharacteristic(s) is emitted. In optional step 410, the previouslygenerated RF emission is acquired, for example with antenna 106 of FIG.1 and processed in a similar manner to processing in step 310.

FIG. 4 similarly shows a set of steps 420, 422, 424, 426 and 428 whereina separate driver, subroutine, method, or dynamic link library (DLL) iscreated containing the modified RF emission containing code and linkedto run with the existing program, with similar results.

FIG. 5A illustrates a flowchart of an exemplary method of finding thefrequency location of the generated RF signal due to any one of hardware(HW), software (SW) and firmware (FW) modification. In step 500, the RFemissions generated from the unmodified hardware, firmware or softwareexisting in a program, ASIC, or FPGA is acquired by an apparatus, thatcan be the apparatus 180 of FIG. 1. Alternatively, the modified softwarewithout the necessary state to cause the modified RF generating code tobe activated is executed. In step 502 the (original, unmodified) RFemissions are acquired, by an apparatus, that can be the apparatus 180of FIG. 1. In step 504, the modified software, firmware or hardwarecontaining the RF code modifications is executed. For example, the IC100 can be connected to supply of power. Or the IC 100 can be operatedin accordance with designed parameters. In step 506, the RF emissions,due to modification(s) are generated and similarly captured by theantenna 106 and processed, for example by the apparatus 180 of FIG. 1.In step 508, the unmodified RF emissions acquired in step 502 and RFemissions acquired in step 506 are compared therebetween, and the RFsignal is located across one or more frequency locations and spans suchas the one shown in FIGS. 6A-B described below. Optional database ofharnessed emission signatures can be generated in step 510 for furtheruse. Emission signature can include one or more characteristics of theemission waveform of FIGS. 6A-B.

FIG. 5B illustrates a flowchart of an exemplary method of verifyingdesired detection and/or categorization of the changed states or usingthe apparatus. In step 512, the database of emissions signatures isacquired. The database of emissions signatures can be the one that wasgenerated in step 510. In step 514, the state(s) of the hardware,software or firmware is(are) changed or modified. New RF emissions arethen harvested in step 516 and desired detection and/or categorizationof the changed states is verified in step 518. It is important to notethat the state changes in 514 may consist of simply turning on thedevice, for example such as the IC 100, under test. In some cases, step514 is optional and may be skipped if the device is already on.

FIG. 6A illustrates a waveform 602 of the RF emissions generated fromstep 502 of FIG. 5 and FIG. 6B illustrates a waveform 608 of RFemissions generated from step 506. A comparison between waveforms 602and 608 shows desired peaks 606 and 604 that are result of the hardware,firmware of software modifications in accordance with methods of FIGS. 3and 4. The peak 600 may be present and is common to both modified andunmodified apparatuses.

FIG. 7 illustrates additional details of the apparatus 180 of FIG. 1.

The receiver 118 is illustrated as comprising a tuner 123 coupled to theLNA 122 and the Analog-To-Digital Converter (ADC) 125 coupled to tuner123. The output from the (ADC) 125 is received at the control unit 126.

In the embodiment of FIG. 7, the control unit 126 is illustrated byfunctional modules. The optional time domain module 760 receives RFsignal in digital form from the ADC 125 and process it in accordancewith a predetermined logic. The output from the time domain module 760is received at the correlation techniques module 762 and is alsoreceived at the processing module 782.

Optional Digital filter 770 also receives RF signal in digital form fromthe ADC 125 for filtering for further use by the frequency domain module772 that is programmed to execute Fourier Transforms on the filtered RFsignal for optional further wavelet de-noisng at optional waveletde-noising module 774. In place of the Fourier transform in 772, othertransforms may be used such as one or more Goertzel algorithm or one ormore Filters such as FIR filters tuned to specific frequenciesdiscovered in step 508 may be used. The optional module 780 may extract,in a response to received processed RF signal from optional waveletde-noising module 774, state-specific features of the RF signal, forexample such as frequency distance between peak 604 and peak 600 or therelative dB height difference between peaks 604 and 600. The processingmodule 782 may comprise, in a response to received processed RF signalfrom time domain module 760, recognition of time domain RF features, forexample such as a periodic increase and decrease of the receivedamplitude at a very specific filtered frequency. The processing module782 may thus comprise a narrow FIR or IIR filter. The output resultsfrom modules 780 and 782 are then received at a module 784 fordetermination of relative criteria being matched. In an example, suchrelative criteria may comprise a degree of relative peak heightdifference between peaks 604 and 600 exceeding a predeterminedthreshold. In an example, such relative criteria may comprise a periodicamplitude change at a specific frequency being within the expected timeperiod maximum and minimum. The results of processing in module 784 canbe then transmitted to outside world 140, stored for further retrievalor displayed on a display (not shown) that can be integrated into thecontrol unit 126 or coupled thereto. It must be noted that both timedomain and frequency domain processing are not necessary, it could beone or the other. As an example, Elements 760, 762 and 782 may beabsent.

FIG. 8 illustrates an embodiment wherein the electromagnetic emission(s)being generated by an electronic device, such as a computer 800. Thecomputer 800 can be any one of a laptop, desk top, tablet, portablecomputer and even a mobile communication device. The electronic device800 can be also a network computer or a server. The electronic device800 may be one motherboard, or any device that comprises one or more ofcircuit boards.

Specifically, when the electronic device 800 is provided as a computer,different locations/components within the computer 800 can emit RFsignals. The emitted RF signals may be of a variety of frequencies and avariety of locations as multiple components may be involved in thecreation of the RF signal, the execution of RF code and the RF signalgeneration. In an example, random access memory (RAM) 802 can generateRF emissions 830 while being accessed, written to, read from, orrefreshed. In an example, RAM memory bus 804 can generate RF emissions.In an example, disk 806 and/or interconnect or trace 808 can generate RFemissions 842. In an example, central processing unit (CPU) 810 cangenerate RF emissions 840. In an example, video controller 818 cangenerate RF emissions 836. In an example, interconnect or line 820 cangenerate RF emissions 838. In an example, input/output (I/O) module 816can generate RF emissions 834. In an example, LED(s) 812 and/orinterconnect or line 814 can generate RF emissions 832.

A single or multiple antennas 106 positioned near or around the separatecomponents may be used to more specifically isolate the location of RFemission. Such antenna(s) 106 may be multiplexed to provide input into asingle receiver 118 or be associated with separate receivers 118.

In an embodiment, a software subroutine or software method can bewritten to perform a memory write access of the same value a specificnumber of iterations, thus causing desired emissions from the RAM memorybus 804 or memory chip assembly emissions 830. The contents of the dataiteratively written, the timing of the data written, and/or the memorylocation of the data written repetitively may thus modify the emissionsin a desired manner so as to effectively modulate it, the RF emissionscontaining the desired data embedded in it.

FIG. 8 also illustrates an embodiment wherein the electromagneticemission(s) being generated by an electronic device, such a circuitboard assembly that incorporates any of the above described devices, forexample such as RAM 830 or CPU 810 modified in accordance withembodiments of modifying the die 220, 250 or the IC 100.

In a further reference to FIGS. 3-8, it is to be recognized thathardware, firmware or software authenticity can be determined bydeliberately creating the RF emission frequency element feature(s) inthe hardware, firmware or software design and later verifying theexistence of the RF emission frequency element feature(s) by receivingthe RF emissions and performing the signal analysis detailed herein andperforming a comparison to expected signal structure, signature and/ordefinition to assess, evaluate, differentiate, and/or determinehardware, firmware or software authenticity likelihood or probability.It is to be further recognized that firmware integrity can also beevaluated in a similar manner as stated herein, wherein specific RFemission elements are designed into the firmware and are expected to beradiating at expected characteristics when compared with a known good orexemplary part or a statistical average frequency response of a set ofknown good parts. It is to be further recognized that software CPUloading can be conveyed by placing a software RF element within asoftware execution loop, and such software RF element periodicity beingmeasured to indicate the execution time of the software execution loop.If the software loop requires more time or less time between RF periodicsignals, an indication of a software change or tampering is recognized.Other timing variations between RF periodic signals can be utilized forencoding and later receiving and decoding other internal device orsystem characteristics such as clock speed slowdown due to CPU heatingcompensation. Specific RF software emission call modification locationsmay be placed directly after the software control flow statements suchas ‘IF’ statements or ‘FOR’ statements to indicate program entry intothat code region or routine, number of loop iterations, or entry intoand execution of especially unusual or anomalous regions such as errorreporting or error trapping regions such as catch clauses. The entryinto these code regions may be indicative of specific data values inmemory being compared or branches into specific codes due to calls orinterrupts. Added wanted or unwanted code, malicious or benign, mayresult in a delay or prolonged period between repeated executions of RFcode. All of these may be detectable.

Thus, the state within the electronic device 100 may be determinedthrough emissions analysis and may consist of hardware authenticity,firmware integrity, software load, data control flow, instruction flow,program state, security state, or the operations of unknown orunexpected code.

The RF code may also be programmed to change operations and hencemeasureable emissions by sensing known factors within the hardware,firmware or software it has been placed in such as issuing an operatingsystem call to determine amount of free memory and performing atransmission for a longer or shorter period based on, proportional to,or a log function of memory available.

The RF code may also be programmed to change operations and hencemeasureable emissions by also performing monitoring of network data,serial data or parallel data patterns received by normal operations orby dedicated listening commands directed towards network data traffic.The RF code may similarly perform enquiry operations over a network andthe RF may respond based on the response data or state of networkinterface. The absence or presence of RF data, or the specific state orform of data influencing the RF emission may be based on specific datapattern(s) received/acquired/listened to by the RF code and may then bereceived by the control unit 126 and processed to match and reflect thecharacteristics or data contained in an external device read and/or incommunication directly or indirectly with the RF over a network.Further, the authenticity of the software, firmware or hardware may bedetermined by an external device transmitting or offering a unique datapattern to the RF hardware or software area, and a specificcorresponding RF pattern response is received by the emission processor126 and compared against a previously acquired or predeterminedstandard. As the specific RF characteristics may be designed to behighly complex and practically unpredictable due to highly complex logicand/or a large number of logic elements used in the creation of the RFemission, the resulting emission may be unique and potentiallyunpredictable and uniquely based on the code sent to the RF elementinside the processor. Thus, because the resulting potentially unique andpotentially unpredictable emission may be only known and measuredpreviously by an entity who previously created the code and measured theprevious emission result, the newly generated re-emission using theprevious pattern would only be known and verifiable by the entity whocreated the pattern and measured the result previously. A plurality ofsuch patterns and substantially unpredictable responses may also beaccumulated, effectively used and only knowable to an entity previouslyin possession of the RF containing device. Different entities maytypically have different patterns and responses to verify the operationof a RF containing device. The electronic device 100 may employself-modifying code capability to further extend its possible number ofstates and corresponding responses. Such self-modifying code capabilitymay be influenced by the patterns it discerns from surrounding data,hardware or network information, and/or may be accumulated over timecreating an ever increasing and more complex challenge response set.Only an entity matching the challenge—response conditions on a similarsystem running in parallel will thus be able to predict a new orcurrently modified-updated response to a challenge. A result of theabove configurations may be an unpredictable specific repeatable uniquechallenge and response set unknowable by another entity and knowableonly to an entity who has previously created or is simultaneouslycreating the challenge and measured the response.

It is to be understood that a substantially identically configuredsystem containing a substantially identical RF and executing in parallelmay be used to generate exemplary RF emissions and form or determine anexemplary basis for emission characteristics of all substantiallysimilarly configured devices. Thus, the specific RF generating deviceresponse need not be initially analyzed in the RF emission domain tolater verify its emission comparison. An exemplary device's resulting RFemission may be previously, currently or later analyzed to determine,verify or predict the expected RF emission response of a different yetsubstantially identically configured unit. The RF emission may berecorded and later verified against an exemplary emission, and need notbe immediately evaluated. The RF emissions may thus be recorded in thetime domain for later FFT processing and analysis orcomparison/verification in the time and/or frequency domain.

As it has been described above, in one or more embodiments, a hardwareof an electronic device is modified, without changing a designedinterface functionality of the electronic device, characteristic(s) ofan electromagnetic energy emittable from the electronic device.

In an example of FIGS. 10A-10D, such modification can be provided by aring oscillator (RO) circuit that is electrically coupled only to apower input or to a power input and a clock input. FIG. 10A illustratesan VHDL firmware 1002 of the exemplary ring oscillator, FIG. 10Billustrates a bloc diagram representation 1004 of the exemplary ringoscillator, FIG. 10C illustrates another bloc diagram representation1004 of the exemplary ring oscillator and FIG. 10D illustrates ahardware microcircuit of the exemplary ring oscillator.

In an embodiment, a firmware FPGA configuration can be employed andadded to similarly transmit a simple device On/Off state through tocomplex RF emissions, wherein complex emissions may be comprised andreliably decodable into a significant number of data bits, typicallyover 8 bits. An RO or a similar circuit may be specifically allocatedand configured for that purpose. The size of the RO may be chosen toconvey the data content. As an example, a 10 stage RO may convey that itis active and the FPGA in which it resides is operational. A separate 20stage RO may convey that it is active and in a different separate FPGAor a different FPGA core in the same FPGA in which it resides and isoperational and powered. Delay elements such as non-inverting gates suchas one or more ‘OR’ gates with both inputs tied together to the outputof one of the inverters and its output tied to the next inverter may bestrategically emplaced in one or more locations to further modify itsemission characteristics. The RO may be extended in functionality to bemodified based on other signals presented to it, thus emitting adifferent pattern dependent on the state of the signals modifying it.Other circuits such as a pseudo-random generator using shift registersand XOR gates or linear-feedback shift register may be alternativelyeasily used as an example.

FIG. 11 illustrates an exemplary nanotube constructed hardware ringoscillator 1102.

FIGS. 13-23 illustrate various examples of means for modifying the abovedescribed die 220, 250, and/or the above described IC 100, withoutchanging a designed interface functionality of the semiconductor device,characteristic(s) of an electromagnetic energy emittable from the die220, 250 and/or IC 100. The RF emissions may be enhanced or modifiedwithout exceeding the specifications of the manufacturer, thus providingdrop in replacement capability and no discernable change to the user ofthe equipment. For the sake of brevity, the circuit is illustrated by atleast a pair of logic (circuit) elements 2313 and 2314 interconnectedwith each other by an interconnect 2002, each having an interconnect2302 with the remaining logic element(s), which can be the unused logicelement 2028 of FIG. 15, another logic element 2315 of FIG. 23 or pin(s)2308 of FIGS. 18-23.

For the sake of reader's convenience, FIG. 12 illustrates an unmodifiedexisting pair of logic elements 2313 and 2314 interconnected with eachother by an unmodified interconnect 2002 and typically connected toother existing logic elements via interconnect 2302.

FIG. 13 illustrates an example of the pair of logic elements 2313 and2314 interconnected with each other by the interconnect 2002 modified bya means, such as a section 2010 with a greater width than a width of theinterconnect 2002. Increase in width of the interconnect 2002 decreasesthe impedance from the interconnect 2002. The section 2010 can bedisposed to one side of the interconnect 2002 and does not have to becentered on such interconnect 2002. Decrease in impedance ischaracterized by a decrease of a peak width, for example such as peak600 of FIG. 6A or peaks 604, 606 of FIG. 6B.

FIG. 14 illustrates an example of the pair of logic elements 2313 and2314 interconnected with each other by the interconnect 2002 modified bya means, such as a plurality of trace elements 2012, spaced apart fromeach other along a length of the interconnect 2002, where one end ofeach trace element 2012 is coupled to the interconnect 2002 and anopposite end of each trace element 2012 is not connected to any otherlogic elements or interconnects.

FIG. 15 illustrates an example of the pair of logic elements 2313 and2314 interconnected with each other by the interconnect 2002 modified bya means, such as a single trace element 2014, where one end of the traceelement 2014 is coupled to the interconnect 2002 and an opposite end ofthe trace element 2014 is not connected to any other logic elements orinterconnects and forms an antenna. The trace element 2014, illustratedas an L-shaped trace element, can be provided in any other shape, aslong as such trace element 2014 only has a connection with theinterconnect 2002.

FIG. 15 also illustrates a means such as an unused logic element 2028whose sole purpose is to create added emissions based on its inputsignal from logic element 2314 and further provide signal for emissionsto an unconnected antenna trace 2030. Logic elements 2313, 2314, 2028may be of FPGA Combinatorial Logic Block type, discrete logic gates, oreven analog components such as amplifiers.

FIG. 16 illustrates an example of the pair of existing logic elements2313 and 2314 interconnected with each other by the interconnect 2002newly modified a means, such as two or more sections 2016, 2018 and2020, each with a greater width than a width of the interconnect 2002.It is also contemplated herewithin that increased width of one section2020 can be smaller than width of one or more other sections 2016, 2018.It is to be understood that a width of an existing (normally specified)interconnect 2002 may be reduced to arrive at the arrangement in FIG.16.

FIG. 17 illustrates an example of the pair of existing logic elements2313 and 2314 interconnected with each other by the interconnect 2002having a greater width than the original interconnect.

FIG. 18 illustrates an example of the pair of existing logic elements2313 and 2314 interconnected with each other by the interconnect 2002with a means, such as a new combinatory modification of FIGS. 14-16,defined by a straight trace element 2012, L-shaped elements 2028, 2030and 2032 and one or more sections 2024, 2026 of increased width. TheL-shaped trace element 2030 can be coupled to the increased widthportion 2024.

FIG. 19 illustrates an example of the logic element 2312 coupled to anI/O pin 2308 with an interconnect 2304. The I/O pin 2308 can be anunused pin during operation of the IC 100. FIG. 19 also illustrates thatthe interconnect 2304 can be modified by a trace element 2340 where oneend of the trace element 2340 is coupled to the interconnect 2002 and anopposite end of the trace element 2340 is not connected to any otherlogic elements or interconnects.

FIG. 20 illustrates an example of the logic element 2312 coupled to twoor more I/O pins 2308 with an interconnect 2304. The I/O pin 2308 can bean unused pin during operation of the IC 100. FIG. 20 also illustratesthat the interconnect 2304 can be modified by a means, such as a traceelement 2340 where one end of the trace element 2340 is coupled to theinterconnect 2002 and an opposite end of the trace element 2340 is notconnected to any other logic elements or interconnects. FIG. 20 furtherillustrates that a new logic output and new trace element 2342 can beadded to the logic element 2314 of the semiconductor device 100. Thelogic element may be a CLB.

FIG. 21 illustrates an example of the pair of existing logic elements2313 and 2314 interconnected with each other by the interconnect 2002and with a further new interconnect 2306 with one or more I/O pins 2308.A new trace element 2246 can be added to modify the RF emissions fromthe IC 100.

FIG. 22 illustrates an example of the existing pair of logic elements2313 and 2314 such as CLBs interconnected with each other by theexisting interconnect 2002 and with a further new interconnect 2306 withone or more I/O pins 2308. Added logic gate 2320 is illustrated as aNAND Gate, but may also be a different logic gate, such as anyone of anExclusive OR or Exclusive NOR, an AND, a NOR, or OR gate will alsogenerate desired new emissions.

FIG. 23 illustrates an example of the pair of existing logic elements2313 and 2315 interconnected with each other by the interconnect 2340and with a further new interconnect 2306 with one or more I/O pins 2308.FIG. 23 also illustrates a existing trace element 2002 coupled to anexisting logic element 2314.

FIG. 24 illustrates a means, such as an exemplary circuit die 2402 abovea conductive layer 2404 positioned below the die 2402 to influence theemissions from the circuit layer 2402 during operation thereof. Afeature, such as notch 2420, can be cut into the conductive layer 2404to further modify emissions from the circuit layer 2402 withoutaffecting interface or operations of the IC 100.

FIG. 25 illustrates a means, such as an exemplary circuit layer 2402below a conductive layer 2404 but connected to the conductive layer 2404with a new interconnect 2405 to modify the emissions from the circuitlayer 2402 during operation thereof.

FIG. 26 illustrates a means, such as an exemplary circuit layer 2402below a conductive layer 2406 which is of a different dimension than theabove described conductive layer 2404 and modifies the RF emissionsdifferently from the RF emissions modified by conductive layer 2404.

FIG. 27 illustrates a means, such as an exemplary circuit layer 2402containing a region 2408 of modified doping which modifies the emissionsfrom the functional circuit layer 2402.

FIG. 28 illustrates an exemplary circuit layer 2402 containing a region2408 of modified doping which modifies the emissions from functionalcircuit layer 2402. A conductive layer 2404 is also connected to aground of the circuit layer 2402 with the interconnect 2410, couplingand modifying emission noise in the ground of the circuit layer 2402.

FIG. 29 illustrates a means, such as an exemplary circuit layer 2402whose emissions are further modified by conductive layer 2412 withadditional features different from conductive layer 2404 and alsoconductive layer 2404 further modifying the emissions. A circuit layer2402 is also connected to conductive plane 2412 with an interconnect tofurther modify emissions. A conductive layer 2406 is below functionalcircuit layer 2402 to further modifying the emissions from the circuitlayer 2402. It must be noted the vertical distance between 2412, 2402,2404 and/or 2406 also modify emissions, as does the layer thicknesses.

FIG. 30 illustrates an example of a substitution of one circuit with afunctionally identical but different circuit to change emissions. Theoriginal NAND circuit 2320 of FIG. 22 is provided as part of a die. TheNAND circuit 2320 can be replaced by a circuit 2502, which is a circuitcontaining two inverters and a NOR gate. Truth table 2320A defines thesates of NAND circuit 2320 and truth tables 2502A defines the states ofthe circuit 2502 with two inverters and a NOR gate. As can be seen fromthe results of both truth tables and as is commonly known to those ofordinary skill in the art, the final results are identical. Region 2320Bhighlights the truth table results of the NAND gate whereas region 2502Bhighlights the truth table results of the circuit 2502. Although theresults are the same, the intermediate logic functions are different andwill result in differing emissions. These differing emissions can beenhanced by a means such as 2502C which represents an antenna stubconnected to the output of 2502 circuit inverter A and located on thedie. Trace element 2502C may also be connected to or replaced by othermeans to enhance emissions such as connecting it to an unused I/O pin ora number of antennas.

FIGS. 31A-D illustrate an example of a hardware modification of theelectronic device of FIGS. 1-2 a containing an RS Flip-Flop with anemission enhancement antenna stub or circuit element 3102 shown in logicgate format of FIG. 31A, with an emission enhancement antenna stub orcircuit element 3108 shown in Mosfet transistor circuit format of FIG.31B, with an emission enhancement antenna element 3102 shown in higherlevel logic symbol format of FIG. 31C, and with an emission enhancementantenna stub shown implemented on a gate in a semiconductor die 3106 ofFIG. 31D.

Thus, in an embodiment, routing circuit traces within a IC 100 may beused to create antenna structures such as interdigital elements in adistributed element filter to create or enhance the emission energylevel and/or frequency characteristics or phase noise of specificemission waveforms.

In a further reference to FIG. 2, the above described trace elements2012, 2014, 2340, referenced with numeral 262, can be coupled to leads210, 224 and even to bonding wires 212, 226. Or, any one of the lead210, 224 or bonding wires 212, 226 can be adapted with portion(s) 260 ofincreased width.

In a further reference to FIG. 8, the examples of FIGS. 13-30 can beemployed to modify RF emissions from a circuit board assembly or even ahigher level assembly, for example as the computer 800. In an example,interconnect portion(s) 866 or a greater width can be provided betweenone or more components. In an example, a trace element 862 or 868 can becoupled to one or more interconnects. In an example, trace elements 864can be coupled, at one end thereof and in a spaced apart relationshipwith each other to one or more interconnects.

FIG. 8A illustrates a printed circuit board (PCB) modified with examplesof FIGS. 13-23. More specifically, new traces 1202, 1204 can be added tothe PCB. One or more traces can be adapted with portions or regions1206, 1208 with a greater width. One or more trace can be modified witha shaped region 1214. One or more trace elements 1212 can be coupled toone or more existing traces.

In an embodiment, routing circuit interconnects to pins that are thenspecifically to be pulled up or pulled down can be used to create newsignature features influenced by the increased electrical path lengthand to increase the amplitude of emissions in general. The addedelectrical length may thus be sufficient to create additional peaks atmultiple frequencies which are of sufficient strength to rise above thereceiver's noise floor.

In an embodiment, a group of circuit interconnects and a group of pinsmay be newly combined by logical functions, for example such as And orOr, and the resulting output be newly used to drive a single pin.Alternatively, they may separately be connected to correspondingseparate unused I/O pins. Alternatively, one or more may separately beconnected to multiple corresponding separate unused I/O pins.

In an embodiment, narrowing or broadening of circuit interconnects willaffect the frequency width of emission peak structures, which naturallyoccurs due to electromigration. This same modification of emissionsignature elements can be achieved by purposefully modifying theinterconnect traces with a broadened or narrowed interconnect betweencomponents, Combinatorial Logic Blocks, gates, or other devices on theIC 100.

In an embodiment, modifying patterns of narrower and/or broader sectionswithin one or more interconnects with varying widths will create aunique emission pattern due to rapid changes in interconnects impedanceas a signal travels down its length.

In an embodiment, modifying the doping of individual gates or patternsof gates within the IC 100 may be used to affect their timing and thusmodify the frequency and amplitude envelope of emitted non-linear mixingproducts.

In an embodiment, narrow trace elements may be placed along the lengthof circuit interconnects, much like whiskers, where the physical spacingof the trace elements and their width will cause emissions withcontrollable waveforms.

In an embodiment, semiconductor device packaging may be modified toalter the frequency or amplitude of existing emissions or introduce newemission signature elements through the placing of a conductive layerson the inner top surface or bottom surface of the packaging.

In an embodiment, the conductive layer can be patterned to furthermodify emission signatures such as a varied layer thickness, added voidsor cutouts in the layer or differing edge geometries and shapes of thelayer.

In an embodiment, multiple such layers may be overlapped and placed inan offset pattern to further modify emissions.

In an embodiment, one or more layers may further be connected to one ormore unused I/O pins which could be either tied up or down, and/or tounused I/O pins connected to circuit interconnects or to gates to modifyemissions. In an embodiment, different technology nodes can be utilizedto introduce features that emit energy with distinct characteristic(s)that can be detected and differentiated by an electromagnetic emissionsensor, for an example such as the apparatus 180. The technology node(also process node, process technology or simply node) is traditionallydefined as the smallest half-pitch of contacted metal 1 lines allowed inthe fabrication process. It is a common metric used to describe anddifferentiate the technologies used in fabricating integrated circuits.Different nodes often imply different circuit generations andarchitectures. Generally, the smaller the technology node means thesmaller the feature size, producing smaller transistors which are bothfaster and use less power. Most recently, due to various marketing anddiscrepancies among foundries, the number itself has lost the exactmeaning it once held. Recent technology nodes such as 45 nm, 32 nm, 22nm, 16 nm, 14 nm, and 10 nm refer purely to a specific generation ofchips made in a particular technology. Circuit elements of differentsizes may not change designed functionality and/or designed interfacesof an electronic device but will change characteristics of the emittedelectromagnetic energy. In an embodiment, the electronic device(s) orthe method(s) utilize different technology node processing techniques tointroduce specific internal die circuit characteristics that can becontrolled to change non-functional or redundant parts of the circuit toprovide a customized emission output that can be used for at least oneof authentication, characterization, the embedding of information,intellectual property watermarking, hardware revisions, program states,or device lineage. Non-limiting examples of such processing techniquescomprise a thinner gate dielectric (thinner oxide layer), differentdoping concentrations, different control(s) of impurities in type andconcentration, different oxidation reaction for dielectric creation,different etching methods, different temperature and processing timesfor impurity diffusions, use of different dopants, use of ionimplantation instead of diffusion.

In an embodiment, the electronic device(s) or the method(s) utilizemeans, features, techniques or steps that evolve over time such that themeasurement of such features can be utilized to measure the time thatthe die, IC, PCB, PCB assembly, or a higher level electronic device hasbeen in use. A non-limiting example comprises implementation of featuresthat are narrow enough that the impedance changes over time the circuitis in use. In one non-example, a trace carrying a specified current canbe narrower than conventionally used so that it degrades faster. Inanother non-limiting example, a radioactive active element can beintegrated into at least a portion of the die or dopant. Thisspecifically designed feature is built into the device so that theemission caused by electrons flowing through said feature changes in aknown way as an aggregated amount of current flows through it over agiven amount of time. Likewise, the feature can be designed that breaksdown or degrades incrementally as voltage is intermittently applied overtime.

In an embodiment, an electronic device can comprise one or more sets orregions of one or more radioactive elements may be integrated into allof, a portion of, a set of gates of, multiple sections of, a section of,or a gate of the substrate, die, feature, dopant, interconnect,dielectric insulator or MEMS element such that its properties change ata specifiable and highly controlled decay rate as the element changes toanother element.

In an embodiment, an electronic device can comprise a dielectricinsulator constructed to gradually become more insulating or lessinsulating, as the resistance of an interconnect, or the gain of a gateelement. This then will cause needed emission changes over the desiredtime period. In an embodiment, an electronic device can comprisemultiple elements and/or isotopes with differing decay rates to craftthe decay curve response and corresponding emission changes.

In an embodiment, an electronic device or method can comprise ionimplantation using specific radioactive or non-radioactive isotopeconcentrations to accurately and selectively achieve the specificallydesired radioactive or nonradioactive element and isotope concentrationlevels and associated electrical and emissions outcomes over devicelifetime.

In an embodiment, electronic device(s) or the method(s) comprisefeature(s), technique(s) or step(s) that change or fail catastrophicallybased on the use characteristics of the electronic device. Such failureof the microstructure(s) does not necessarily cause failure of theelectronic device, but provides an indication that an event, forexamples such as an Electrostatic Discharge (ESD), a radiation dose, atemperature exposure out of specification, a pressure, a humidity, or achemical exposure has occurred.

In an embodiment, electronic device(s) can comprise a fuse (not shown)that can be coupled to lead 210 and that can be configured to besusceptible to the environmental effect(s), such that a previouslyradiating designed-in feature was turned off or a previouslynon-radiating designed-in feature was turned on via the fuse.

In an embodiment, electronic device(s) comprise a fuse (not shown) thatis configured to convey, via designed-in radiating features, a widerange of characteristics of the electronic device that are at least oneof a permanent, an intermittent, a gradual, an event-driven, a Boolean(on or off) or a temporary.

In an embodiment, the electronic device comprises one or more MicroElectroMechanical System (MEMS) sensors that are at least one ofintegrated with at least one of a die or IC, wherein said MEMSindications can be translated into features that result inelectromagnetic emissions with distinct characteristics such that theseemissions can be detected by an external sensor.

In an embodiment, MEMS sensors disposed external to the die or ICwherein the MEMS indications or electronic signals from MEMS andconveyed thru unused input pins to emission circuitry provide a higherlevel of measurement acuity that can be characteristically conveyed to asensor or an apparatus that is measuring the electromagnetic emissionsof the electronic device in a non-contact manner.

In an embodiment, a semiconductor device comprises a semiconductorsubstrate; one or more circuits disposed on the semiconductor substrate;and a means for modifying, without changing a designed interfacefunctionality of the semiconductor device, characteristic(s) of anelectromagnetic energy emittable from the semiconductor device.

A feature of this embodiment is that the means comprises one or moretrace elements within the one or more circuits, each of the one or moretrace elements with one end thereof being directly coupled tointerconnect between two circuit elements within the one or morecircuits and with an opposite end thereof being terminated withoutcoupling to any one of trace(s) between circuit elements within the oneor more circuits.

A feature of this embodiment is that the means comprises trace elementsspaced at a predetermined distance from each other along a length of atleast one circuit interconnect, each of the trace elements with one endthereof being directly coupled to the at least one interconnect and withan opposite end thereof being terminated without coupling to any one ofinterconnect(s) between circuit elements within the one or morecircuits.

A feature of this embodiment is that the means comprises at least oneinterconnect between at least a pair of circuit elements in thesemiconductor device, the at least one interconnect with one or moreregions of a smaller or larger width, the one or more regions affectingwidth of peak structure(s) of emitted electromagnetic energy.

A feature of this embodiment is that the means comprises one or moreinterconnect with a varying width, the varying width modifying impedanceof the one or more interconnect.

A feature of this embodiment is that the means comprises a modificationor doping of gate(s) and/or pattern(s) of gates within the semiconductordevice resulting in a timing change of the gate(s) and/or the pattern(s)of gates, the timing change modifying frequency and amplitude envelopeof non-linear mixing products.

A feature of this embodiment is that the means comprises at least onetrace element coupling at least one circuit element in the circuit withan unused I/O pin in the semiconductor device.

A feature of this embodiment is that the means comprises at least oneinterconnect between at least two circuit elements in the semiconductordevice, with one or more regions of a smaller or larger width, the oneor more regions affecting width of peak structure(s) of emittedelectromagnetic energy; and one or more trace elements within the one ormore circuits, each of the one or more trace elements with one endthereof being directly coupled to the one or more regions of a smalleror larger width and with an opposite end thereof being terminatedwithout coupling to any one of trace(s) between circuit elements withinthe one or more circuits.

A feature of this embodiment is that the means comprises one or moretrace elements within the one or more circuits, each of the one or moretrace elements with one end thereof being directly coupled to aninterconnect between two circuit elements within the one or morecircuits and with an opposite end thereof being terminated withoutcoupling to any one of interconnect(s) between circuit elements withinthe one or more circuits; one or more region in one or moreinterconnects between circuit elements, the one or more region with adifferent width than a remaining portion of the one or moreinterconnect; and at least one trace element coupling at least onecircuit element in the circuit with an unused I/O pin in thesemiconductor device.

A feature of this embodiment is that the means comprises a doping regionin one or more layers of the semiconductor device, the doping regionconfigured to change the characteristic(s) of the electromagnetic energyemittable from the semiconductor device.

A feature of this embodiment is that the doping region is on a layercarrying the one or more circuits thereon.

A feature of this embodiment is that the means comprises a notch in aconductive layer in the semiconductor device, the notch configured tochange the characteristic(s) of the electromagnetic energy emittablefrom the semiconductor device.

A feature of this embodiment is that the means comprises a change inconductor composition, changing the electron velocity within theconductor and modifying the circuit timing.

A feature of this embodiment is that the means comprises an interconnectbetween a conductive layer and a layer carrying the one or morecircuits, the interconnect configured to change the characteristic(s) ofthe electromagnetic energy emittable from the semiconductor device.

A feature of this embodiment is that the means comprises a conductivelayer positioned above or below a layer carrying the one or morecircuits thereon, the conductive layer having a smaller size than a sizeof the layer carrying the one or more circuits thereon.

A feature of this embodiment is that the means comprises a conductivelayer positioned above a layer carrying the one or more circuitsthereon, the conductive layer comprising a notch; a conductive layerpositioned below the layer carrying the one or more circuits thereon,the conductive layer having a smaller size than a size of the layercarrying the one or more circuits thereon; and an interconnect betweenthe layer carrying the one or more circuits thereon and the conductivelayer positioned below the layer carrying the one or more circuitsthereon.

A feature of this embodiment is that the means comprises replacement ofone circuit logic element with another circuit logic element changing anintermediate logic function(s) without changing end logic function(s).

In an embodiment, a method of authenticating an electronic devicecomprises the steps of modifying any one of a software, hardware orfirmware of the electronic device to generate emissions ofelectromagnetic energy with one or more preselected characteristics;connecting the electronic device to at least a supply of operatingvoltage; receiving, with an antenna coupled to a receiver, the emissionsof the electromagnetic energy; and determining, with a control unit, ina response to received emissions of the electromagnetic energy apresence of the one or more preselected characteristics.

In an embodiment, a method of marking a semiconductor device comprisesthe steps of modifying, without changing a designed interfacefunctionality of the semiconductor device, a structure of thesemiconductor device to emit preselected characteristic(s) of anelectromagnetic energy; operating the semiconductor device to emit theelectromagnetic energy; and confirming, with a control unit, a presenceof the preselected characteristic(s) in a response to a receipt ofemitted electromagnetic energy.

In an embodiment, a method of authenticating an electronic device,comprising a processor that executes a program, comprises the steps ofacquiring a source code in the program; modifying one or more portionsof the source code; compiling a new program with the modified sourcecode; executing the new program; emitting electromagnetic energy fromthe electronic device during execution of the program, theelectromagnetic energy with characteristic(s) associated with the one ormore modified portions of the source code; and authenticating theelectronic device in a response to a receipt of the emittedelectromagnetic energy with the characteristic(s) associated with theone or more modified portions of the source code.

In an embodiment, a method of authenticating an electronic device,comprising a processor that executes a program, comprises the steps ofacquiring a source code in the program; modifying one or more portionsof the source code; and compiling a new program with the modified sourcecode;

In an embodiment, a method of authenticating an electronic device,comprising a processor that executes a program, comprises the steps ofacquiring a source code in the program; modifying one or more portionsof the source code; compiling a new program with the modified sourcecode; executing the new program; emitting electromagnetic energy fromthe electronic device during execution of the program, theelectromagnetic energy with characteristic(s) associated with the one ormore modified portions of the source code; and authenticating theelectronic device in a response to a receipt of the emittedelectromagnetic energy with the characteristic(s) associated with theone or more modified portions of the source code.

In an embodiment, a method of authenticating a semiconductor devicecomprises the steps of acquiring a design of the semiconductor device;modifying one or more portions of the semiconductor device;manufacturing a new die containing the one or more modified portions;connecting power and clock signals to the semiconductor device; emittingelectromagnetic energy from the semiconductor in a response to the powerand clock signals, the electromagnetic energy with characteristic(s)associated with the one or more modified portions of the semiconductordevice; and authenticating the electronic device in a response to areceipt of the emitted electromagnetic energy with the characteristic(s)associated with the one or more modified portions of the semiconductordevice.

In an embodiment, a method of authenticating a semiconductor devicecomprises the steps of acquiring a design of the semiconductor device;modifying one or more portions of the semiconductor device;manufacturing a new die containing the one or more modified portions;and packaging the new die into an electronic device.

In an embodiment, a non-transitory computer readable recording mediumhas recorded thereon a program for executing any of the above methods.

In an embodiment, a system for authenticating an electronic devicecomprises a means for modifying, without changing a designed interfacefunctionality of the electronic device, characteristic(s) of anelectromagnetic energy emittable from the electronic device; an antennaconfigured to acquire the electromagnetic energy signal emitted from theelectronic device; a receiver coupled to the antenna and configured toconvert the acquired electromagnetic energy signal into a digital form;and a control unit coupled to the receiver, the control unit configuredto process the converted electromagnetic energy signal and identify thecharacteristic(s).

In an embodiment, an apparatus for authenticating an electronic devicecomprises an antenna configured to acquire the electromagnetic energysignal emitted from the electronic device; a receiver coupled to theantenna and configured to convert the acquired electromagnetic energysignal into a digital form; and a control unit coupled to the receiver,the control unit configured to process the converted electromagneticenergy signal and identify characteristic(s) of the electromagneticenergy due to a modification of the electronic device in a manner thatdoes not change a designed interface functionality of the electronicdevice.

A feature of this embodiment is that the control unit comprises one ormore processors; and a non-transitory computer readable mediumcomprising executable instructions that, when executed by the one ormore processors, cause the one or more processors to identify thecharacteristic(s).

In an embodiment, a printed circuit board (PCB) assembly comprises aPCB; one or more electronic devices mounted on the PCB; interconnectsbetween the one or more electronic device; and a means for modifying,without changing a designed interface functionality of the PCB assembly,characteristic(s) of an electromagnetic energy emittable from the PCBassembly.

A feature of this embodiment is that the means comprises one or moretrace elements within the one or more electronic device, each of the oneor more trace elements with one end thereof being directly coupled to aninterconnect between two circuit elements within the one or moreelectronic device and with an opposite end thereof being terminatedwithout coupling to any one of interconnect(s) between circuit elementswithin the one or more electronic device.

A feature of this embodiment is that the means comprises trace elementsspaced at a predetermined distance from each other along a length of theinterconnect(s), each of the trace elements with one end thereof beingdirectly coupled to an interconnect between two electronic devices andwith an opposite end thereof being terminated without coupling to anyone of interconnect(s) between the one or more electronic devices.

A feature of this embodiment is that the means comprises one or more offrom the interconnects with one or more regions of a smaller or largerwidth, the one or more regions affecting width of peak structure(s) ofemitted electromagnetic energy.

A feature of this embodiment is that the means comprises one or moreinterconnects with a varying width, the varying width modifyingimpedance of the one or more trace.

A feature of this embodiment is that the means comprises a modificationor doping of gate(s) and/or pattern(s) of gates within the one or moreelectronic devices resulting in a timing change of the gate(s) and/orthe pattern(s) of gates, the timing change modifying frequency andamplitude envelope of non-linear mixing products.

A feature of this embodiment is that the means comprises at least onetrace element coupling at least one electronic device in the circuitwith an unused I/O connection on the PCB.

A feature of this embodiment is that the means comprises one or moreinterconnects with one or more regions of a smaller or larger width, theone or more regions affecting width of peak structure(s) of emittedelectromagnetic energy; and one or more trace elements on the PCB, eachof the one or more trace elements with one end thereof being directlycoupled to the one or more regions of a smaller or larger width and withan opposite end thereof being terminated without coupling to any one ofinterconnect(s) between the one or more electronic devices.

A feature of this embodiment is that the means comprises one or moretrace elements within on the PCB, each of the one or more trace elementswith one end thereof being directly coupled to an interconnect betweentwo electronic devices and with an opposite end thereof being terminatedwithout coupling to any one of interconnect between the electronicdevices; one or more region in one or more interconnect between a pairof electronic devices, the one or more region with a different widththan a remaining portion of the one or more interconnect; and at leastone trace element coupling at least one electronic device with an unusedI/O connection on the PCB.

In an embodiment, an electronic device comprises one or more printedcircuit board (PCB) assemblies, each comprising a PCB, electronicdevices mounted on the PCB, and interconnects between the one or moreelectronic device; and a means for modifying, without changing adesigned interface functionality of the PCB assembly, characteristic(s)of an electromagnetic energy emittable from the electronic device.

In an embodiment, an integrated circuit (IC) device comprises a casing;one or more input/output connections on or extending from an interiorsurface of the casing; one or more dies within the casing; leads betweenthe one or more die and the one or more input/output connections; bodingwires, each coupling each lead to the one or more die; and a means formodifying, without changing a designed interface functionality of theIC, characteristic(s) of an electromagnetic energy emittable from theIC.

A feature of this embodiment is that the means comprises one or moretrace elements, each of the one or more trace elements with one endthereof being directly coupled to a lead and with an opposite endthereof being terminated without coupling to any one of leads.

A feature of this embodiment is that the means comprises one or moretrace elements, each of the one or more trace elements with one endthereof being directly coupled to a bonding wire and with an oppositeend thereof being terminated without coupling to any one of bondingwires.

A feature of this embodiment is that the means comprises trace elementsspaced at a predetermined distance from each other along a length of atleast one lead, each of the trace elements with one end thereof beingdirectly coupled to the at least one lead and with an opposite endthereof being terminated without coupling to any one of leads.

A feature of this embodiment is that the means comprises at least onelead with one or more regions of a smaller or larger width, the one ormore regions affecting width of peak structure(s) of emittedelectromagnetic energy.

A feature of this embodiment is that the means comprises one or moreleads with a varying width, the varying width modifying impedance of theone or more interconnect.

A feature of this embodiment is that the means comprises one or morebonding wires with a varying width, the varying width modifyingimpedance of the one or more interconnect.

A feature of this embodiment is that the means comprises a modificationor doping of gate(s) and/or pattern(s) of gates within the one or moredies resulting in a timing change of the gate(s) and/or the pattern(s)of gates, the timing change modifying frequency and amplitude envelopeof non-linear mixing products.

In an embodiment, a method is provided for identifying a software changeor a software tampering within a central processing unit (CPU), themethod comprises the steps of placing a software RF emission elementwithin a software execution loop; periodicity measuring the software RFemission element to determine an execution time of the softwareexecution loop between RF emission periodic signals; measuring adifference between the determined execution time and a threshold; anddetermining the software change or tempering based on the measureddifference.

The above described exemplary embodiments take advantage of the factthat low-level emissions of a high degree of complexity and potentialencoded data content can be generated using no additional cost andlittle added CPU time, silicon area, or FPGA gates.

In an embodiment, a chip comprises individual circuits whose conductiveor insulative circuit features are modified by one or more radioactiveisotopes in one or more locations to modify the function of the chip orone or more of its circuits so that its operation is irrevocably timecontrolled to enable, enhance, degrade or disable circuit capabilitiesor functionality before, after or during a pre-specified time period.

In an example, a gate dielectric insulator may be doped via ion beamdeposition and ion beam focus and selection for deposition in a veryspecific region or regions with a radioactive isotope of sufficientconcentration, half-life and particle charge characteristic (electron,positron, electron capture, etc.) to change the gate from anon-functioning gate for approximately 6 months to a functioning gateapproximately 6 months after manufacture. Thus, the chip or chip featuremay not be functional until a specified period of time has elapsed.Further, a different element or isotope may be doped into the gatedielectric insulator to degrade or change elements far more slowly, forexample such that after approximately 5 years the gate may again becomenon-functional. The function, chip or feature relying on that gate isthus available for a specific duration, a specific start time andspecific stop time. This creates a self-disabling feature and capabilityin electronic devices.

The above can separately be placed on various gates, regions,conductors, MEMS sensors, insulators to selectively enable and/ordisable them at pre-specified times. Elements and isotopes selected maycreate characteristics such as but not limited to increased insulating,increased conducting, or more chemically degrading characteristics intoany or all constituent components of a die.

In an example, a light sensor may be pre-deposited or pre-doped with aisotope creating electric noise via beta decay that severely limits itsvision capability during the first half-life of 2 months of the isotope,becoming gradually usable and considered fully usable after 6 months.

In an example, the needed doping concentration may only gradually‘appear’ as the deposited isotope decays into the useful needed dopingelement needed for circuit operation. Alternatively, the needed dopingconcentration may be configured to gradually radioactively decayrendering the gate gradually useless. The doping in the circuitry andthe circuitry design may be configured to thus automatically switch overto a different functioning or similar functioning circuit withdifferent, greater or fewer features at and/or during a pre-specifiedtime period. Proper selection of elements, isotopes, half-lives withincircuits, gates and chip design allow for unlimited capabilitysequencing or options available.

The above examples also provide a means for modifying conductive orinsulative circuit features of one or more circuits of the chip by oneor more radioactive isotopes in one or more locations to modify thefunction of the chip or one or more of its circuits so that itsoperation is irrevocably time controlled to enable, enhance, degrade ordisable circuit capabilities or functionality before, after or during apre-specified time period.

The above examples also define method(s) for modifying conductive orinsulative circuit features of one or more circuits of the chip by oneor more radioactive isotopes in one or more locations to modify thefunction of the chip or one or more of its circuits so that itsoperation is irrevocably time controlled to enable, enhance, degrade ordisable circuit capabilities or functionality before, after or during apre-specified time period.

The above described exemplary embodiments promulgate speed of thesemiconductor device modification, by essentially minimizing additionalhardware design. Further, existing hardware specifications need not bescrutinized and adhered to, in adding the RF transmit embodimentsdisclosed herein. In typical common known hardware designs wheretransmitter functionality is added or retrofitted, additional hardwarecan be specifically chosen based on electrical, mechanical, cost, andphysical specifications and constraints. The design time requiredconforming to those constraints and interface to the additional hardwareis significantly higher than the method and apparatus described in theinstant invention.

The above described exemplary embodiments quickly allow the constructionof a means to transmit states or data from deep within a program,semiconductor logic device, or FPGA, without the typical need for logicconveyance of the data to peripheral output signal physical hardwarelines and the output of the signals on an established medium, in anestablished format, at an established frequency, or other typicallynecessary details. The state information or data can be transmitted witha minimum of effort, from anywhere within a program or hardware device,and indicative of any state, memory or register variable value, hardwaremodule activity, software module activity, software module being called,hardware module being enabled or the like. As such, the instantinvention may also be a useful tool for debugging software, firmware orhardware. As an example, RF emission elements can be deliberately placedto be activated or deactivated depending on the initialization state,sequence, or code section being executed. As a more specific example,deliberately placed RF emission elements may be easily and/or quicklyplaced in various device drivers or bootstrap code elements, indicatingsequence of operations or milestones reached in the process, thus beingactivated substantially in sequence as a system bootup or startupprogresses. Should the time gap(s) between one expected RF emissionelement and a second or series of RF emission startup elements beprolonged, not be in the expected order, or not occur at the expectedtiming separations, indications of a software problem, software change,hardware problem, or even software or hardware version may be received.In this manner, diagnostics may be embedded into software, firmware orhardware without requiring use, maintenance or allocation of additionalsystem resources, and without necessarily requiring interface toexternal software or hardware elements for the communication of thosestates or state transitions such as a logging area in memory or on disk.Another advantage of this approach is the platform independencecapability in some cases, as the same source code or VHDL code may becompiled on any system or from any FPGA. The specific new emissionfrequencies, shapes, profiles, envelopes and/or signatures generated mayvary to a degree between systems (ex. Linux, Android, Apple IoS, orWindows) and/or between hardware platforms (Intel or AMD, Xilinx orLattice), but the individually distinct and discernable patterns createdwould remain present, locatable and useful.

In an embodiment, any of the above described methods can be implementedin the form of software stored on a computer-readable non-transitoryinformation storage medium such as an optical or magnetic disk, anon-volatile memory (e.g., Flash or ROM), RAM, and other forms ofvolatile memory. The information storage medium may be an internal partof the computer, a removable external element coupled to the computer,or unit that is remotely accessible via a wired or wireless network.

In an embodiment, any of the above described methods can be written (ortake form) as a computer program and can be implemented in general-usedigital computers that execute the programs using a computer readablestorage and/or recording medium. In addition, the structure of data usedin the method can be written on a computer readable recording medium byusing several units. Examples of the computer readable storage and/orrecording medium include magnetic storage media (e.g., ROM, RAM, USB,floppy disks, hard disks, etc.), optical recording media (e.g., CD-ROMs,or DVDs), PC interface (e.g., PCI, PCI-express, WiFi, etc.), etc. Inother words, in the context of this document, a computer readablestorage and/or recording medium may be any tangible medium that cancontain, or store a program and/or data for use by or in connection withan instruction execution system, apparatus, or device.

Any combination of one or more computer readable storage medium(s) maybe utilized. A computer readable storage medium may be embodied as, forexample, an electronic, magnetic, optical, electromagnetic, infrared, orsemiconductor system, apparatus, or device, or other like storagedevices known to those of ordinary skill in the art, or any suitablecombination of computer readable storage mediums described herein.

In an embodiment, the computer may comprise the receiver 118.

In an embodiment, any of the above described methods can be implementedby single or multiple algorithms.

Persons of ordinary skill in the art may appreciate that, in combinationwith the examples described in the embodiments herein, units andalgorithm steps can be implemented by electronic hardware, computersoftware, or a combination thereof. In order to clearly describe theinterchangeability between the hardware and the software, compositionsand steps of every embodiment have been generally described according tofunctions in the foregoing description. Whether these functions areperformed using hardware or software depends on particular applicationsand design constraints of the technical solutions. A person skilled inthe art may use different methods to implement the described functionsfor each specific application. However, such implementation should notbe considered as beyond the scope of the present invention. As anexample, the same circuit modifications may be made in an ASIC, FPGA, orcustom logic device.

Computer program code for carrying out operations for aspects of variousembodiments may be written in any combination of one or more programminglanguages, including an object oriented programming language, such asJava, Smalltalk, C++, or the like, and conventional proceduralprogramming languages, such as the “C” programming language or similarprogramming languages. In accordance with various implementations, theprogram code may execute entirely on the user's computer, partly on theuser's computer, as a stand-alone software package, partly on the user'scomputer and partly on a remote computer or entirely on the remotecomputer or server. In the latter scenario, the remote computer may beconnected to the user's computer through any type of network, includinga local area network (LAN) or a wide area network (WAN), or theconnection may be made to an external computer (for example, through theInternet using an Internet Service Provider).

The flowchart and/or block diagrams in the figures help to illustratethe architecture, functionality, and operation of possibleimplementations of systems, methods and computer program products ofvarious embodiments. In this regard, each block in the flowchart orblock diagrams may represent a module, segment, or portion of code,which comprises one or more executable instructions for implementing thespecified logical function(s). It should also be noted that, in somealternative implementations, the functions noted in the block may occurout of the order noted in the figures. For example, two blocks shown insuccession may, in fact, be executed substantially concurrently, or theblocks may sometimes be executed in the reverse order, depending uponthe functionality involved. It will also be noted that each block of theblock diagrams and/or flowchart illustration, and combinations of blocksin the block diagrams and/or flowchart illustration, can be implementedby special purpose hardware-based systems that perform the specifiedfunctions or acts, or combinations of special purpose hardware andcomputer instructions.

It will be understood that various blocks of the flowchart illustrationsand/or block diagrams, and combinations of blocks in the flowchartillustrations and/or block diagrams, can be implemented by computerprogram instructions. These computer program instructions may beprovided to a processor of a general purpose computer, special purposecomputer, or other programmable data processing apparatus to produce amachine, such that the instructions, which execute via the processor ofthe computer or other programmable data processing apparatus, createmeans for implementing the functions/acts specified in the flowchartand/or block diagram block or blocks.

Many of the elements described in the disclosed embodiments may beimplemented as modules. A module is defined here as an isolatableelement that performs a defined function and has a defined interface toother elements. The modules described in this disclosure may beimplemented in hardware, software in combination with hardware,firmware, wetware (i.e hardware with a biological element) or acombination thereof, all of which are behaviorally equivalent. Forexample, modules may be implemented as a software routine written in acomputer language configured to be executed by a hardware machine (suchas C, C++, Fortran, Java, Basic, Matlab or the like) or amodeling/simulation program such as Simulink, Stateflow, GNU Octave, orLab VIEWMathScript. Additionally, it may be possible to implementmodules using physical hardware that incorporates discrete orprogrammable analog, digital and/or quantum hardware. Examples ofprogrammable hardware comprise: computers, microcontrollers,microprocessors, application-specific integrated circuits (ASICs); fieldprogrammable gate arrays (FPGAs); and complex programmable logic devices(CPLDs). Computers, microcontrollers and microprocessors are programmedusing languages such as assembly, C, C++ or the like. FPGAs, ASICs andCPLDs are often programmed using hardware description languages (HDL)such as VHSIC hardware description language (VHDL) or Verilog thatconfigure connections between internal hardware modules with lesserfunctionality on a programmable device. Finally, it needs to beemphasized that the above mentioned technologies are often used incombination to achieve the result of a functional module.

The chosen exemplary embodiments of the claimed subject matter have beendescribed and illustrated, to plan and/or cross section illustrationsthat are schematic illustrations of idealized embodiments, for practicalpurposes so as to enable any person skilled in the art to which itpertains to make and use the same. As such, variations from the shapesof the illustrations as a result, for example, of manufacturingtechniques and/or tolerances, are to be expected. It is thereforeintended that all matters in the foregoing description and shown in theaccompanying drawings be interpreted as illustrative and not in alimiting sense. For example, a region illustrated or described as flatmay, typically, have rough and/or nonlinear features. Moreover, sharpangles that are illustrated may be rounded. Thus, the regionsillustrated in the figures are schematic in nature and their shapes arenot intended to illustrate the precise shape of a region and are notintended to limit the scope of the present claims. It will be understoodthat variations, modifications, equivalents and substitutions forcomponents of the specifically described exemplary embodiments of theinvention may be made by those skilled in the art without departing fromthe spirit and scope of the invention as set forth in the appendedclaims.

When used herein, the terms “adapted” and “configured” mean that theelement, component, or other subject matter is designed and/or intendedto perform a given function. Thus, the use of the terms “adapted” and“configured” should not be construed to mean that a given element,component, or other subject matter is simply “capable of” performing agiven function but that the element, component, and/or other subjectmatter is specifically selected, created, implemented, utilized,programmed, and/or designed for the purpose of performing the function.It is also within the scope of the present disclosure that elements,components, and/or other recited subject matter that is recited as beingadapted to perform a particular function may additionally oralternatively be described as being configured to perform that function,and vice versa. Similarly, subject matter that is recited as beingconfigured to perform a particular function may additionally oralternatively be described as being operative to perform that function.

It be understood that when an element is referred to as being “on”another element, it can be directly on the other element or interveningelements may be present therebetween. In contrast, when an element isreferred to as being “directly on” another element, there are nointervening elements present. As used herein, the term “and/or” includesany and all combinations of one or more of the associated listed items.

It will be understood that, although the terms “first,” “second,”“third” etc. may be used herein to describe various elements,components, regions, layers and/or sections, these elements, components,regions, layers and/or sections should not limited by these terms. Theseterms are only used to distinguish one element, component, region,layer, or section from another element, component, region, layer orsection. Thus, “a first element,” “component,” “region,” “layer,” or“section” discussed below could be termed a second element, component,region, layer, or section. without departing from the teachings herein.

Spatially relative terms, such as “beneath,” “below,” “lower,” “above,”“upper,” and the like, may be used herein for ease of description todescribe one element or feature's relationship to another element(s) orfeature(s) as illustrated in the figures. It will be understood that thespatially relative terms are intended to encompass differentorientations of the device in use or operation in addition to theorientation depicted in the figures. For example, if the device in thefigures is turned over, elements described as “below” or “beneath” otherelements or features would then be oriented “above” the other elementsor features. Thus, the exemplary term “below” can encompass both anorientation. of above and below. The device may be otherwise oriented(rotated 90 degrees or at other orientations) and the spatially relativedescriptors used herein interpreted accordingly.

Unless otherwise defined, all terms (including technical and scientificterms) used herein have the same meaning as commonly understood by oneof ordinary skill in the art to which this disclosure belongs. It willbe further understood that terms, such as those defined in commonly useddictionaries, should be interpreted as having a meaning that isconsistent with their meaning in the context of the relevant art and thepresent disclosure, and will not be interpreted in an idealized oroverly formal sense unless expressly so defined herein.

Unless otherwise stated, specific embodiments provide electronicdevice(s) or component(s) with modified characteristic(s) of the emittedelectromagnetic energy without modification(s) to designed functionallyor interface of the electronic device(s) or component(s). Similarly,unless otherwise stated specific embodiments provide methods to modifiedcharacteristic(s) of the emitted electromagnetic energy from anelectronic device or component(s)without modification(s) to designedfunctionally or interface of such electronic device(s) or component(s).

Although the subject matter has been described in a combination with RFemissions, the disclosed embodiments will apply to devices emittingmicrowave emissions, millimeter wave emissions and terahertz waveemissions.

It should be appreciated that reference throughout this specification to“one embodiment” or “an embodiment” means that a particular feature,structure or characteristic described in connection with the embodimentis included in at least one embodiment of the present invention.Therefore, it is emphasized and should be appreciated that two or morereferences to “an embodiment” or “one embodiment” or “an alternativeembodiment” in various portions of this specification are notnecessarily all referring to the same embodiment or the same variation.Furthermore, the particular features, structures or characteristics maybe combined as suitable in one or more embodiments of the invention.

Similarly, it should be appreciated that in the foregoing description ofembodiments of the invention, various features are sometimes groupedtogether in a single embodiment, figure, or description thereof for thepurpose of streamlining the disclosure aiding in the understanding ofone or more of the various inventive aspects. This method of disclosure,however, is not to be interpreted as reflecting an intention that theclaimed subject matter requires more features than are expressly recitedin each claim. Rather, as the following claims reflect, inventiveaspects lie in less than all features of a single foregoing disclosedembodiment. Thus, the independent claims following the detaileddescription are hereby expressly incorporated into this detaileddescription.

Any element in a claim that does not explicitly state “means for”performing a specified function, or “step for” performing a specifiedfunction, is not to be interpreted as a “means” or “step” clause asspecified in 35 U.S.C. §112, ¶6. In particular, any use of “step of” inthe claims is not intended to invoke the provision of 35 U.S.C. §112,¶6.

Anywhere the term “comprising” is used, embodiments and components“consisting essentially of” and “consisting of” are expressly disclosedand described herein.”

Furthermore, the Abstract is not intended to be limiting as to the scopeof the claimed invention and is for the purpose of quickly determiningthe nature of the claimed invention.

What is claim is:
 1. A semiconductor device, comprising: a semiconductorsubstrate; one or more circuits disposed on said semiconductorsubstrate; and a means for modifying, without changing a designedinterface functionality of said semiconductor device, characteristic(s)of an electromagnetic energy emittable from said semiconductor device.2. The semiconductor device of claim 1, wherein said means comprises oneor more trace elements within said one or more circuits, each of saidone or more trace elements with one end thereof being directly coupledto interconnect between two circuit elements within said one or morecircuits and with an opposite end thereof being terminated withoutcoupling to any one of trace(s) between circuit elements within said oneor more circuits.
 3. The semiconductor device of claim 1, wherein saidmeans comprises trace elements spaced at a predetermined distance fromeach other along a length of at least one circuit interconnect, each ofsaid trace elements with one end thereof being directly coupled to saidat least one interconnect and with an opposite end thereof beingterminated without coupling to any one of interconnect(s) betweencircuit elements within said one or more circuits.
 4. The semiconductordevice of claim 1, wherein said means comprises at least oneinterconnect between at least a pair of circuit elements in saidsemiconductor device, said at least one interconnect with one or moreregions of a smaller or larger width, said one or more regions affectingwidth of peak structure(s) of emitted electromagnetic energy.
 5. Thesemiconductor device of claim 1, wherein said means comprises one ormore interconnect with a varying width, said varying width modifyingimpedance of said one or more interconnect.
 6. The semiconductor deviceof claim 1, wherein said means comprises a modification or doping ofgate(s) and/or pattern(s) of gates within said semiconductor deviceresulting in a timing change of said gate(s) and/or said pattern(s) ofgates, said timing change modifying frequency and amplitude envelope ofnon-linear mixing products.
 7. The semiconductor device of claim 1,wherein said means comprises at least one trace element coupling atleast one circuit element in said circuit with an unused I/O pin in saidsemiconductor device.
 8. The semiconductor device of claim 1, whereinsaid means comprises: at least one interconnect between at least twocircuit elements in said semiconductor device, with one or more regionsof a smaller or larger width, said one or more regions affecting widthof peak structure(s) of emitted electromagnetic energy; and one or moretrace elements within said one or more circuits, each of said one ormore trace elements with one end thereof being directly coupled to saidone or more regions of a smaller or larger width and with an oppositeend thereof being terminated without coupling to any one of trace(s)between circuit elements within said one or more circuits.
 9. Thesemiconductor device of claim 1, wherein said means comprisesreplacement of one circuit logic element with another circuit logicelement changing an intermediate logic function(s) without changing endlogic function(s).
 10. An integrated circuit (IC) device, comprising: acasing; one or more input/output connections on or extending from aninterior surface of said casing; one or more dies within said casing;leads between said one or more die and said one or more input/outputconnections; boding wires, each coupling each lead to said one or moredie; and a means for modifying, without changing a designed interfacefunctionality of said IC, characteristic(s) of an electromagnetic energyemittable from said IC.
 11. The IC device of claim 10, wherein saidmeans comprises one or more trace elements, each of said one or moretrace elements with one end thereof being directly coupled to a lead andwith an opposite end thereof being terminated without coupling to anyone of leads.
 12. The IC device of claim 10, wherein said meanscomprises one or more trace elements, each of said one or more traceelements with one end thereof being directly coupled to a bonding wireand with an opposite end thereof being terminated without coupling toany one of bonding wires.
 13. The IC device of claim 10, wherein saidmeans comprises trace elements spaced at a predetermined distance fromeach other along a length of at least one lead, each of said traceelements with one end thereof being directly coupled to said at leastone lead and with an opposite end thereof being terminated withoutcoupling to any one of leads.
 14. The IC device of claim 10, whereinsaid means comprises at least one lead with one or more regions of asmaller or larger width, said one or more regions affecting width ofpeak structure(s) of emitted electromagnetic energy.
 15. A printedcircuit board (PCB)assembly, comprising: a PCB; one or more electronicdevices mounted on said PCB; interconnects between said one or moreelectronic device; and a means for modifying, without changing adesigned interface functionality of said PCB assembly, characteristic(s)of an electromagnetic energy emittable from said PCB assembly.
 16. ThePCB assembly of claim 15, wherein said means comprises one or more traceelements within said one or more electronic device, each of said one ormore trace elements with one end thereof being directly coupled to aninterconnect between two circuit elements within said one or moreelectronic device and with an opposite end thereof being terminatedwithout coupling to any one of interconnect(s) between circuit elementswithin said one or more electronic device.
 17. The PCB assembly of claim15, wherein said means comprises trace elements spaced at apredetermined distance from each other along a length of saidinterconnect(s), each of said trace elements with one end thereof beingdirectly coupled to an interconnect between two electronic devices andwith an opposite end thereof being terminated without coupling to anyone of interconnect(s) between said one or more electronic devices. 18.The PCB assembly of claim 15, wherein said means comprises one or moreof from said interconnects with one or more regions of a smaller orlarger width, said one or more regions affecting width of peakstructure(s) of emitted electromagnetic energy.
 19. The PCB assembly ofclaim 15, wherein said means comprises one or more interconnects with avarying width, said varying width modifying impedance of said one ormore trace.
 20. The PCB assembly of claim 15, wherein said meanscomprises a modification or doping of gate(s) and/or pattern(s) of gateswithin said one or more electronic devices resulting in a timing changeof said gate(s) and/or said pattern(s) of gates, said timing changemodifying frequency and amplitude envelope of non-linear mixingproducts.